1. Field of the Invention
The invention relates to semiconductor technology and in particular to memory devices.
2. Description of the Related Art
Non-volatile memory devices are currently in wide use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. Flash EEPROM devices, however, enable erasure of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the transistor. The electron transfer is initiated by either hot electron injection or Fowler-Nordheim (F-N) tunneling. One important dielectric material for the fabrication of the floating-gate electrode is an oxide-nitride-oxide (ONO) structure. During programming, electrical charges are transferred from the substrate to the silicon nitride layer in the ONO structure and trapped therein. Moreover, non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice the information of a conventional EEPROM in a memory array of equal size. A left bit and right bit are stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell.
Referring to FIG. 1, a related art introduces an operating method for an EEPROM device 10, namely a SONOS (silicon-oxide-nitride-oxide-silicon) device, having a non-conducting charge trapping dielectric, such as a silicon nitride layer 20, sandwiched between two silicon oxide layers 18 and 22 acting as electrical insulators. In view of localized trapping electron charge capability of the silicon nitride layer 20, the EEPROM device 10 is capable of storing two bits of information, i.e., there are two bits per cell. A left bit and a right bit are stored in physically different areas of the silicon nitride layer 20, near left and right regions of the memory cell 10, respectively.
To program the right bit, for example, programming voltages are applied to the gate electrode 24 and drain 16 and hot electrons are injected into and trapped in the charge trapping layer 20 in the region near the drain defined by the dashed circle 23. Correspondingly, the threshold voltage of the portion of the channel under the trapped charge increases as more and more electrons are injected into the nitride layer. Similarly, the left bit is programmed by applying programming voltages to the gate electrode 24 and source 14. Hot electrons are injected into and trapped in the charge trapping layer 20 in the region defined by the dashed circle 21. The threshold voltage of the portion of the channel under the trapped charge comprising the left bit increases as more and more electrons are injected into the nitride layer.
Using the right bit as an example, one erasure technique simultaneously applies a negative potential to the gate electrode 24 and a positive potential to the drain 16 such that holes from the drain 16 flow into the charge trapping nitride layer 20 via the bottom oxide 18, combining with the electrons trapped in the charge trapping nitride layer 20. The left bit is erased in a similar fashion except that a positive potential is applied to the source 14 rather than the drain 16. Using the right bit as an example, a second well known technique simultaneously applies a positive voltage potential to the gate electrode 24 and zero potential, i.e., ground, to the drain 16 such that holes from the gate electrode 24 flow through the top oxide 22 into the charge trapping nitride layer 20, combining with the electrons trapped in the charge trapping nitride layer 20. The left bit is erased in a similar fashion with zero potential applied to the source 14.
As the integrity of integrated circuits increases, the size of semiconductor devices, such as the width of the gate electrode 24 shown in FIG. 1, is reduced, bring the right bit and the left bit closer to each other. Finally, the right bit and the left bit potentially “unify” as a single bit, such that the memory device is no longer a two-bit EEPROM.
Referring to FIG. 2, S and D respectively indicate positions of the source 14 and drain 16 shown in FIG. 1, the solid curves 21e and 23e respectively show the electron distribution in the dashed circles 21 and 23 during programming of the left bit and the right bit of the device shown in FIG. 1, and the dashed curves 21h and 23h respectively show the hole distribution in the dashed circles 21 and 23 during erasure of the left bit and the right bit of the device shown in FIG. 1. The deviation between the electron and hole distributions causes incomplete combination of electrons and holes during erasure of the left bit and the right bit of the device shown in FIG. 1, resulting in charge accumulation upon completion of a program-erase cycle, negatively affecting the reliability of the memory device.